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Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

LPDDR2 IP woes

I am using the Quartus Lite application from 17.1 to 22.1, all varieties have been tested. In essence I am porting a design that was tested on a: Terasic Technologies Cyclone V GX Starter Kit ...
Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

I have used signal-tap to investigate some of the logic levels:

global_reset_n = 1

soft_reset = 1

pll_ref_clk is running at 50MHz

afi_clk is running and is the sampling clock

The differences are that:

local_init_done = 0

local_cal_fail = 0

local_cal_success = 0

The 3 signals above suggest the calibration hasn't started.

Anyone have any ideas on how I can move forward would be greatly appreciated.