Occasional ContributorI did not take into consideration the Preamble, SFD, and FCS for my calculation. This then explains the required clock cycles between Avalon ST "packets".
Occasional ContributorHi Dlim,
Thank you for these suggestions.
I can say that I did read the first chapter that you mentioned about connecting the clocks correctly and have set these up to be synchronous in my simulation. I had not seen that AN before; however, having read through it, there is no new hints/tips that might suggest what is causing this issue.
I wonder if what I'm seeing is due to the built in averaging of the IPG feature in the 10G variant? To test the behaviour I send, to the core on the 64b AVST interface, 999 packets with a gap between them of 3 clock cycles. Then I send 1 packet after a gap of two.
I repeat this cycle 20 times for good measure and after the 12 cycle, when the 13th packet with a gap of only 2 is sent to the core, I start to see the ready signal deasserting after every time I send the packet with the shorter gap before it.
Thank you very much for your help @Deshi_Intel
James
Occasional ContributorI did not take into consideration the Preamble, SFD, and FCS for my calculation. This then explains the required clock cycles between Avalon ST "packets".
