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JHaye4's avatar
JHaye4
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Low Latency Ethernet 10G MAC Minimum Inter Packet Gap

I am simulating a bidirectional 10G Base-R example design MAC with the only change being "Use legacy Ethernet 10G MAC Avalon Streaming Interface" option enabled. In my testbench the core has all conf...
  • JHaye4's avatar
    JHaye4
    5 years ago

    I did not take into consideration the Preamble, SFD, and FCS for my calculation. This then explains the required clock cycles between Avalon ST "packets".

Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,

Just wonder have you refer to

I also found additional AN735 that talks about the migration guideline and highlight the IP difference to user

Thanks.

Regards,

dlim

  • JHaye4's avatar
    JHaye4
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi Dlim,

    Thank you for these suggestions.

    I can say that I did read the first chapter that you mentioned about connecting the clocks correctly and have set these up to be synchronous in my simulation. I had not seen that AN before; however, having read through it, there is no new hints/tips that might suggest what is causing this issue.

    I wonder if what I'm seeing is due to the built in averaging of the IPG feature in the 10G variant? To test the behaviour I send, to the core on the 64b AVST interface, 999 packets with a gap between them of 3 clock cycles. Then I send 1 packet after a gap of two.

    I repeat this cycle 20 times for good measure and after the 12 cycle, when the 13th packet with a gap of only 2 is sent to the core, I start to see the ready signal deasserting after every time I send the packet with the shorter gap before it.

    Thank you very much for your help @Deshi_Intel

    James

    • JHaye4's avatar
      JHaye4
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      I did not take into consideration the Preamble, SFD, and FCS for my calculation. This then explains the required clock cycles between Avalon ST "packets".