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Renardo18's avatar
Renardo18
Icon for New Contributor rankNew Contributor
4 years ago
Solved

Low Latency 100G Ethernet bring-up : read 0xdeadc0de

Hi, I am trying to replace the 40G Ethernet IP by the 100G in a new FPGA that I just bought (FPGA is stratix 10 : 1SX280HU2F50E1VGAS). The link is not coming up, I am looping back 2 Ethernet por...
  • Deshi_Intel's avatar
    Deshi_Intel
    4 years ago

    HI,


    One of the possibility is you are reading the reg from invalid/incorrect memory region.


    You may want to check the reg address memory mapping in your design again.


    Thanks.


    Regards,

    dlim


Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

HI,


One of the possibility is you are reading the reg from invalid/incorrect memory region.


You may want to check the reg address memory mapping in your design again.


Thanks.


Regards,

dlim