local_burstbegin on DDR2 HP

I'm debugging an issue where in simulation, my system can read/write to DDR2 via the DDR2 HP controller, however on a Stratix II GX chip, it cannot (specifically, the pci express dev kit).

Looking at the examples in the user guide, everything appears right. When I read, I get an rdata valid signal assertion, but the read data is "0xFFFFFFFF". Previously, I wrote 0's to the same address. I don't know if the issue is reading, or writing, but there is something wrong.

In the user guide for the IP core, it says that the local_burstbegin signal only needs to be used for local_size >= 2. In my implementation, local_size = 1 always. I'm using the Avalon-MM interface.

In order for the simulation to work, I have to have local_burstbegin asserted whenever I do a read/write. Based on what I read in the user guide, I shouldn't be using local_burstbegin at all.

Does anyone know if local_burstbegin actually needs to be used for local_size = 1? Or, have any suggestions as to what the problem could be? Timing passes (no violations at all). Testbench works fine.

Thanks,

baver