L- and H-tile Avalon® Streaming IP for PCI Express - x16 simulation

Hi,

If the ltssm is stuck in detect.quite stage, You may refer to the Fault Tree Analysis table.

It probably cause by the Reset issue, Ref clock Issue

https://community.intel.com/t5/FPGA-Wiki/FTA-PCI-express/ta-p/735993

Also, based on my understanding, it is possible to simulate two PCIe IP using PIPE interface.

To simulate two PCIe Streaming IPs using the PIPE interface in Quartus, you would need to create a testbench that includes two PCIe controllers, each with its own PHY, and connect them together using the PIPE interface. You would then use the Quartus Simulation Tool to run the simulation.

Let me know if you need any further clarification on this.

Regards,

Wincent_Intel