L- and H-tile Avalon® Streaming IP for PCI Express - x16 simulation
Hello,
I'm trying to simulate an x16 L- and H-tile Avalon® Streaming IP for PCI Express.
Using: Quartus Prime Version 22.2.0 Build 94 06/08/2022 SC Pro Edition.
For this, both a Root Port and endpoint are instantiated and connected via the serial interface.
A 100MHz reference clock is provided and resets driven as described in the User Guide.
However, the ltssm never exits the Detect Quiet stage.
Interestingly, this is only the case when generating the IP Cores using 16 lanes. When using e.g. 8 lanes, the link training completes as expected and transaction layer packets can be sent from the rootport to the endpoint.
Hence my questions:
- Can two x16 IP Cores be simulated against each other using the serial interface? I.e. connecting rx_in/tx_out of the root port with tx_out/rx_in of the end point.
- Setting bit at index 0 of the test_in input port to 1b'1' supposedly "turns on diag_fast_link_mode to speed up simulation" according to the User Guide . This indeed causes the ltssmstate of the root port to walk through the link training sequence. Also one can observe transmission on the serial interface, supposedly PCIe TS1 and TS2 Ordered Sets for link training. However the state goes back to Detect Quiet after Configuration Complete. What does diag_fast_link_mode mean?
- Can two PCIe Streaming IP for PCI Express alternatively be simulated against each other using the PIPE interface?
Thank you in advance!
