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SBinS's avatar
SBinS
Icon for New Contributor rankNew Contributor
6 years ago

JTAG to Avalon MM Bridge

Hi, I am working on the tutorial and get stuck at the master_write or master_read command line. I'm using the Quartus Prime Lite 19.1 and Platform Designer (formerly Qsys), I wrote those line command...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

Do all the previous commands (before master_write_32) run successfully with no warnings or errors? That error usually indicates that System Console can't access the service type (master) that you've set up with the get_service_paths command. Also note that the open_service command is deprecated and that claim_service should be used. I don't think open_service will cause an error, but it should not be used anymore.

It would also be helpful to see your Platform Designer system and how the JTAG to Avalon bridge is connected and how the addressing is set up.

#iwork4intel

  • SBinS's avatar
    SBinS
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hello there,

    So I am following this tutorial

    https://www.intel.com/content/www/us/en/develop/articles/intel-cyclone-10-lp-fpga-kit-build-a-custom-hardware-system.html

    Everything can easily followed but up until "Generate header file", I started getting error when I tried to enter this command line

    BAT_PATH {}

    tcl> if {$tcl_platform(platform) == "windows"} {

    > set BAT_PATH [glob -join $quartus(quartus_rootpath) .. nios2eds {Nios II Command Shell.bat}]

    > }

    Alternatively it worked when I generate it using NIOS II shell but the problem is for the next line where there is need for global join

    # execute sopc-create-header-files to generate the header files

    tcl> eval exec -ignorestderr ${BAT_PATH} ${SCHF_PATH} soc_system.sopcinfo --output-dir qsys_headers

    # read the header file for master_0 into a TCL variable

    tcl> set master_0_header [read [open [glob -join qsys_headers master_0.h] r]]

    I cannot find any suggestion on the web so I proceed with the next tutorial in this link

    https://www.intel.com/content/www/us/en/develop/articles/intel-cyclone-10-lp-fpga-kit-debug-hardware-with-system-console.html

    When I tried to insert master read and write command, the error said

    "Jun 01, 2020 8:04:30 PM com.altera.debug.coreWARNING: This transaction has not completed in 10 seconds. System Console will keep trying for 50 more seconds.

    ----after 50 seconds----

    java.lang.Exception: master_read_32: This transaction did not complete in 60 seconds. System Console is giving up.

    Someone told me that it is because of the IP (JTAG to Avalon) is not responding and the clock is missing.

    Can you advice me on this? Here I attached the Platform Designer .qsys that I worked on based on the links above. Thanks

    Regards

    Sayed