JESD204B debug

Hi,

Thanks for sharing the signaltap. As I compare the failure signaltap with the "JESD204B Link Initialization" in the user guide, it seems like the rx_pcs_data_valid was not asserted after the reset_n is released. Without the data valid assertion, the subsequent link up event is not taking place. We can further narrow down our debugging to the PMA portion. Note that the SI is still an area of suspect.

To facilitate further debugging on this, please do the following:

1. Use signaltap to check the PHY status signals to further narrow down the problem to PMA. You may refer to table "PHY Status Signals for All Supported Devices Except Intel Stratix 10 E-tile Devices" in the JESD204B IP user guide for the list of signals to monitor if you are not using S10 E-Tile.

2. Tap the signals in "PHY Status Signals for Intel Stratix 10 E-tile Devices" if you are using S10 E-Tile.

3. What are the specific Quartus and FPGA part that you are using?

4. Please try to look into the serial loopback test which I mentioned in my previous post.

Please let me know if there is any concern. Thank you.