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waterst's avatar
waterst
Icon for New Contributor rankNew Contributor
4 years ago
Solved

JESD204B (Agilex F-Tile) v1.0.0 - Support Logic Generation Error (Quartus 22.1)

Hi there, I've recently upgraded to Quartus 22.1 to enable generation of the JESD204B IP for Agilex F-Tile devices. Following IP customisation, I am able to perform the 'Generate HDL' step but the...
  • ZH_Intel's avatar
    ZH_Intel
    4 years ago

    Hi Toby,


    Good day.

    Thank you for your patience.


    >Is this an issue with the 22.1 release?

    At the moment, there is no known issue such as the error(21842).

    We have tried with Intel® Quartus® Prime Software version 22.1 from our side but did not manage to replicate the error.


    We suggest you to try generate our design example as per the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide to see if this error still happen.


    If the error still occur, please do attach your design here for us to have a look.


    Thank you.


    Best Regards,

    ZulsyafiqH_Intel


ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi Toby,


Good Day.

Apologize for the delayed response.

Due to some the technical error, we have just receive your reply.


>Do you know if there is a separate document to cover this?

I'm afraid that we only have1 User Guide for Agilex at the moment.


>Is it possible to clear the accepted solution on this post as it has not been resolved?

I have tried to remove it but I cannot due to system limitation.

After further discussion with internal team, it is found that I can only change the accepted solution but not remove it. Hence, once we have come to the final solution, I will change it.


May I know your Agilex F-Tile device type? The product variant?

So that I can create a sample Example Design from my side for you to test on your side.


Thank you.


Best Regards,

ZulsyafiqH_Intel