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CHebl's avatar
CHebl
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6 years ago

JESD204 IP-Core occasionally receives wrong data in internal loopback mode

I'm currently trying to implement the JESD204-IP Core to receive data from an ADC on an Arria 10 using Quartus Prime v18.1. To test the receiver I implemented both channels (TX and RX) of the Transce...
Nathan_R_Intel's avatar
Nathan_R_Intel
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6 years ago

Chris,

Since there is no Rx 8B10B decode error, then there is more confidence that the received data is correct. Hence, this should be a Signaltap capture error. Could you describe how you oversampled the output data? My suggestion was to use a clock that is twice the speed of the recovered clock as sampling clock of Signaltap.

Regards,

Nathan