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CHebl
New Contributor
6 years agoJESD204 IP-Core occasionally receives wrong data in internal loopback mode
I'm currently trying to implement the JESD204-IP Core to receive data from an ADC on an Arria 10 using Quartus Prime v18.1. To test the receiver I implemented both channels (TX and RX) of the Transce...
Nathan_R_Intel
Contributor
6 years agoHie,
Apologies for the delayed first response. Since you mentioned there is no errors being asserted, this could be a signal tap sampling capture error. However to be certain, could you double check if the 8B10B decode errors are asserted. If yes, then this could be mean the incoming data is corrupted; suggesting intermitently something happens either at the channel level or device level to corrupt the data.
If no, then this could mean the signaltap capture on the Rx side is incorrect. Please check for timing errors related to signaltap path or use a 2xfater sampling clock on signaltap.
Regards,
Nathan