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AKhel1's avatar
AKhel1
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6 years ago

Issues using ST-Avalon root port on Stratix 10 MX development Kit

Hello, I am developing a root port PCIe IP on my Stratix 10 MX development kit (1SM21BHU2F53E1VG) and I have some issues. When i compile my IP I got this error messages in Fitter step: Error(14566...
Nathan_R_Intel's avatar
Nathan_R_Intel
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6 years ago

Hie Amine,

Sorry for the delayed response. I have determined your issue. Please assign the p-n per the Stratix 10 MX development kit schematics. The HIP will detect the polarity is inverse and enable polarity inversion in the buffer. Your error is caused by placing the pin in the inversed location.

Please change as following:

pcie_rx_rc[0] PIN_BH7

pcie_rx_rc[1] PIN_BJ5

pcie_rx_rc[2] PIN_BG5

pcie_rx_rc[3] PIN_BF7

pcie_rx_rc[4] PIN_BE5

pcie_rx_rc[5] PIN_BD7

pcie_rx_rc[6] PIN_BB7

pcie_rx_rc[7] PIN_BC5

Regards,

Nathan