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Altera_Forum
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9 years ago

Issue with CIC filter implementation using DSP builder.

Hi, I'm implementing a 2 stage CIC decimation(/1000) filter using the DSP builder but not using the CIC block rather using adder and substractor to implement it. As per my calculation the CIC f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi Kaz,

Thanks for your reply. I forgot to put the downsampler over there. I'm updating a new screenshot. I'm getting a dc at the output but with random spikes. I thought of using a PLL as a clock divider to be placed between the integrator and the comb section but it won't allow me to add PLL block. Please have a look at the attachments and kindly suggest something. Thanks a lot.

Note: 1st subplot is the final output