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Honored Contributor
Honored ContributorIssue with 245 Fifo sync mode
Dear All, I am actually working on a communication chain between a FPGA and a FT2232H chip. So, the goal is to send a file from PC to FPGA, store it in a FIFO memory and then receive the se...
Altera_ForumHonored Contributor
Honored ContributorThank you for your answer.
I checked and, yes, all the timing specs are met and all the signals are synchronized to the clock (60 MHz) delivered by the FT2232H chip. From what I have observed, the lost byte does not occur in the FPGA side. Indeed, when a lose occurs, this lose is not detected in the FPGA. All the sequence of data leave the FPGA correctly. So, the problem can come from the fact that the FT2232H chip tells that he can receive a byte (his fifo is not full) but this is not true in this case I dont know how to resolve this. But the problem can come from somewhere else.
