Issue with 245 Fifo sync mode

Thank you for your answer.

I checked and, yes, all the timing specs are met and all the signals are synchronized to the clock (60 MHz) delivered by the FT2232H chip.

From what I have observed, the lost byte does not occur in the FPGA side. Indeed, when a lose occurs, this lose is not detected in the FPGA. All the sequence of data leave the FPGA correctly.

So, the problem can come from the fact that the FT2232H chip tells that he can receive a byte (his fifo is not full) but this is not true in this case I dont know how to resolve this. But the problem can come from somewhere else.