Is there a way for CvP over PCIe to do CvP update?
Reading the CvP over PCIe, it looks like Intel has moved away from CvP Update Mode for all PCIe Gen3 IP and the Arria 10 does not support CvP Update at all for any PCIe Gen. Is there a way to use the...
If you look carefully on ug_cvp.pdf file it is using the same method as the S10 CvP update. The reason that it need a physical partition in order for Quartus to split the design optimization correctly where the periphery region is not being accidentally modified.
Hi, on page 36 of the ug-s10-cvp.pdf the Figure 16 and Figure 17 shows the requirement to create Logic Lock Region and lock the region with the origin, width, and height for physical placement. However, ug-cvp.pdf does not use Logic Lock Region and shows nothing to specify the region’s origin/width/height. Instead, ug-cvp.pdf uses “Design Partition”, which is a different menu item below the “Logic Lock Region” item.
The ug-cvp.pdf specifies two regions at first: periphery region and core region, then it further divides the core region down to static region and reconfigurable region, and only the reconfigurable region needs to be designated as a Design Partition with multi-persona capability. If ug-cvp.pdf does not omit anything in the document, its advantage is that it does not require user to specify the region with origin, width, and height. In other words, Quartus handles the regions sizing and placement by itself. In ug-s10-cvp.pdf, the sizing and placement of the region has to be done by users.
The ug-cvp.pdf I downloaded is UG-01101 dated 2016.10.31. Does Intel have a newer version of the ug-cvp.pdf that is updated to change the way how its Cvp Update is done?
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