Forum Discussion
Altera_Forum
Honored Contributor
15 years agoFvM was quicker than me to state that the type real is not synthesizable. (I needed to check first ...)
Any function described by a for loop will ultimately end up being combinatorial (and thus usually too slow), pipelining to speed it up is however plain manual labor. New VHDL constructs to make this easier would be very interesting -> System-VHDL?