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Hi,
1) Test it :-) and give answer. I think it not accepted by Quartus.
2) In VHDL, I use assertions. there may be an equivalent in Verilog.
++
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1) wiseguy .. :) I knew I could test it -- but that only yields results very particular to one software (Quartus), and moreover, one version of that software (I'm using v7.2) ... I was hoping for a more "Verilog Lanugage Rules" type answer... :)
Anyways, QII v7.2 gives the following error:
Error (10232): Verilog HDL error at ***v(**): index 1 cannot fall outside the declared range [-1:0] for vector "****"
2) Did some checking -- Verilog doesn't seem to support Assertions yet ... :( maybe we can hope for a future revision to include support..
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Is it going to be a custom component in SOPC Builder? If it is, you can add ranges to generics in your hw.tcl file that will notify the user and stop him/her from generating the project if the value is outside the range.
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Nope-- not using SOPC builder this time around .. no need for this project.. thanks though!
..dane
Honored Contributor
