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Altera_Forum's avatar
Altera_Forum
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17 years ago

is there a mechanism in verilog to validate parameter values?

I'm working on a very simple verilog module that has a parameter for the width of an input signal. I'll be using "[WIDTH-1:0] nomenclature for register instantiations, for instance.. Two quest...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

1) Test it :-) and give answer. I think it not accepted by Quartus.

2) In VHDL, I use assertions. there may be an equivalent in Verilog.

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