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Altera_Forum
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12 years ago

Is it save to use the PIO in QSYS

Hello, I have several PIOs in my QSYS design to communicate with some of my own designed IPs. My IPs mostly use other clock signals than the PCIe-Clock and are therefore not synchronized to t...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Hi Steffen,

If your test source was a register actually hard coded to make either 0xAA..AA or 0x55..55 it seems possible that Quartus has implemented it as just a pair of wires carrying '1' or '0' connected to all the PIO inputs. It may even be a single wire with a toggling signal, with inverters built into alternate PIO outputs. The time differences involved to each bit might then be in the psec region, so the chance of a transition event would be pretty small. Beware of optimisations. I think your test needs more randomness to check for safety of the readings.

Regards,

Simon