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Paul44's avatar
Paul44
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2 years ago

IP Example Design (DDR4 IP) Synth only Missing Libraries?

Hi, please could I ask a question. Using Quartus prime pro (v24.1) to generate a basic DDR4 IP design targeting an Agilex7 device. Early stages of design. Just wishing to instantiate ddr4 ip block ...
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HubertG's avatar
HubertG
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2 years ago

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.