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Paul44's avatar
Paul44
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2 years ago

IP Example Design (DDR4 IP) Synth only Missing Libraries?

Hi, please could I ask a question. Using Quartus prime pro (v24.1) to generate a basic DDR4 IP design targeting an Agilex7 device. Early stages of design. Just wishing to instantiate ddr4 ip block ...
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HubertG's avatar
HubertG
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2 years ago

Hi Paul44, can I request some of the details of the info from you which written in the earlier message ?

Thanks

Hubert