Forum Discussion
Paul44
New Contributor
2 years agoIP Example Design (DDR4 IP) Synth only Missing Libraries?
Hi, please could I ask a question. Using Quartus prime pro (v24.1) to generate a basic DDR4 IP design targeting an Agilex7 device. Early stages of design. Just wishing to instantiate ddr4 ip block ...
HubertG
Contributor
2 years agoHi Paul44, I have received your question ^^ Can I request some time from you to let me check and confirm with the team and get back to you soon ?
-Always at your service-
Thanks
Hubert