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Adithiya_R's avatar
Adithiya_R
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1 year ago
Solved

Intel P-tile Avalon ST BAR0 addr_offset

Hi Everyone, I am using Ptile-pcie ip in endpoint mode, Gen4 1x8 256 bit configuration and Quartus 23.4 I have an issue regarding bar0_write with a different offset. I tried the following tlp [Da...
Pcie
  • VenT_Altera's avatar
    VenT_Altera
    1 year ago

    Hi Adithiya_R,

    Thanks for sharing your observation.


    This is an expected behavior. The TLP header and data are dword aligned. There is no workaround to change the address alignment that I am aware of.


    If you use the BAM and BAS modes on P-Tile, the AVMM address is aligned to the natural width of the data. For example, if the data width is 64B, the addresses must align to 64B.


    Thanks.

    Best Regards,

    Ven


Adithiya_R's avatar
Adithiya_R
Icon for New Contributor rankNew Contributor
1 year ago

Hi Ventt
We are trying to run ptile pcie in end_point mode + user_logic, but during timing analysis "coreclkout_hip" the one generated by HIP ( hard pcie_ip core) and fed to user_logic , is not visible in the "all clocks report"

what would be the procedure to enable this?

In Gen 3 1x8 256 bit with 250 Mhz mode, Quartus is not able to automatically detect this "coreclkout_hip" and do the timing analysis of user_logic that's synchronous with respect to this clock