Forum Discussion
Occasional ContributorIntel Opencl FPGA blocking channel
No, independent channel operations happen sequentially and at an order decided by the compiler. This is why mem_fence(CLK_CHANNEL_MEM_FENCE) is provided to avoid potential deadlocks resulting from channel operation re-ordering by the compiler. In your example it is very much possible that the channel operations might result in a deadlock if they are re-ordered by the compiler. You should make sure to use a mem_fence(CLK_CHANNEL_MEM_FENCE) both between the two channel read operations and the two channel write operations to avoid this.
Frequent ContributorCertainly not; if a certain channel order is required to avoid deadlocks, then you should use a mem_fence to enforce the ordering. If not (i.e. channel operations can be safely re-ordered), then let the compiler decide the order of the operations.
Occasional ContributorBy deadlock you meant which channel operations are stalling maximum amount of time?
