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TKapi's avatar
TKapi
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3 years ago

Intel MAX 10 FFT bad works

Hi, I am using Quartus 22.1 (the problem was in 21.1 the same). IP configuration is attached. The first anomaly: sink_sop and sink_eop are every 128clk, but the source_sop and source_eop are ran...
TKapi's avatar
TKapi
Icon for New Contributor rankNew Contributor
3 years ago

Hi,

I tried differet FFT settings and different FPGA size.

FPGA: 10M25SAE144I7G

Now, I have another, but similar, problem. The signal source_sop has double size (it takes two clocks of clk). Is it normal?

ZOOM:

What could be the cause? Has the clk signal any restrictions? My clk frequency is 390 Hz.

Thank you, Tomas