New ContributorIntel L-/H-Tile Avalon Streaming for PCI Express IP used as a master (DMA Board --> PC)
Hi,
I am using the Intel L-/H-Tile Avalon Streaming for PCI Express IP on the Stratix 10 NX chip.
For my application, I developed a DMA in the FPGA that can write data into PC's memory. I was working with Xilinx's FPGA and I want to adapt it on Intel's Stratix.
The Xilinx's IP owns 4 interfaces :
* cq : PC is master and is sending read/write requests.
* cc : link for the FPGA to answer read requests initiated by PC
* rq : FPGA is master and we can initiate read/write requests
* rc : link for the PC to answer read requests initiated by FPGA
From my understanding, Intel's IP has only 2 interfaces : Rx and Tx. It is similar to cq and cc interfaces so PC is master. Is it possible to have the Tx link initiating requests ? I haven't seen anything about this topic in the documentation.
PS : I don't want to use Multi Channel DMA for PCI Express as the IP takes a lot of resources.
