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I have experimented more with this issue and found the intel design example located here:
I extracted the project archive, compiled it, generated the simulation IP setup scripts (Tools > Generate Simulator Setup Script for IP) and top level verilog representation of the block diagram design file (EDA Netlist Writer).
I then ran this through the simulation and achieved the following result:
The description of the example project claims that "When both the FFT and iFFT are operating as expected, Cosine data will be recovered and observed at the iFFT output."
The output seen in the simulator is not the cosine wave as expected.
I have attempted this in both:
Quartus 17.1 Prime Pro* + ModelSim - Intel FPGA Starter Edition 10.5c
Quartus 21.4 Prime Pro+ QuestaSim - Intel FPGA Edition 2021.3
Both attempts yield an unexpected output - source_real and source_imag are not cosine waves.
(below is the output from the QuestaSim simulation)
*Questa 17.1 Prime Pro fails a full compile - the log can be seen below. I have checked and the file it claims to be unable to load does exist in the directory listed.
Problem Details Error: Internal Error: Sub-system: DCALC, File: /quartus/ddb/dcalc/dcalc_bcm_modules_cache.cpp, Line: 116 Could not load pdb file - c:/intelfpga_pro/17.1/quartus/common/devinfo/cyclone10gx/ddb_cyclone10gx_io_48_3v_tile-ff-3-0-hs_model_debug Stack Trace: 0x5d410: DCALC_TIMING_MODULES_CACHE::get_model + 0x21dbc (ddb_dcalc) 0x2f2cb: DCALC_TIMING_NETLIST_MANAGER_IMPL::load_model + 0x43 (ddb_dcalc) 0x41631: <lambda_27927aa62a013f38f2f5db62a47234ba>::operator() + 0x71 (ddb_dcalc) 0x41446: tbb::interface6::internal::partition_type_base<tbb::interface6::internal::auto_partition_type>::execute<tbb::interface6::internal::start_for<tbb::blocked_range<int>,tbb::internal::parallel_for_body<<lambda_27927aa62a013f38f2f5db62a47234ba>,int>,tbb::auto_partitioner const >,tbb::blocked_range<int> > + 0x6e (ddb_dcalc) 0x413d0: tbb::interface6::internal::start_for<tbb::blocked_range<int>,tbb::internal::parallel_for_body<<lambda_27927aa62a013f38f2f5db62a47234ba>,int>,tbb::auto_partitioner const >::execute + 0x20 (ddb_dcalc) 0x1c1f3: tbb::internal::custom_scheduler<tbb::internal::IntelSchedulerTraits>::local_wait_for_all + 0x193 (tbb) at d:\sj\nightly\17.1\240\w64\acds\quartus\extlibs64\tbb\tbb42_20131118oss_altera\src\tbb\custom_scheduler.h:472 0x19afe: tbb::internal::arena::process + 0x18e (tbb) at d:\sj\nightly\17.1\240\w64\acds\quartus\extlibs64\tbb\tbb42_20131118oss_altera\src\tbb\arena.cpp:105 0x16867: tbb::internal::market::process + 0xf7 (tbb) at d:\sj\nightly\17.1\240\w64\acds\quartus\extlibs64\tbb\tbb42_20131118oss_altera\src\tbb\market.cpp:479 0x10eac: tbb::internal::rml::private_worker::run + 0x6c (tbb) at d:\sj\nightly\17.1\240\w64\acds\quartus\extlibs64\tbb\tbb42_20131118oss_altera\src\tbb\private_server.cpp:283 0x1111a: tbb::internal::rml::private_worker::thread_routine + 0x5a (tbb) at d:\sj\nightly\17.1\240\w64\acds\quartus\extlibs64\tbb\tbb42_20131118oss_altera\src\tbb\private_server.cpp:240 0x24f7e: _beginthreadex + 0x106 (MSVCR120) 0x25125: _endthreadex + 0x191 (MSVCR120) 0x154df: BaseThreadInitThunk + 0xf (KERNEL32) 0x485a: RtlUserThreadStart + 0x2a (ntdll) End-trace Executable: quartus_fit Comment: None System Information Platform: windows64 OS name: Windows 10 OS version: 10.0 Quartus Prime Information Address bits: 64 Version: 17.1.0 Build: 240 Edition: Pro Edition