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ushermark's avatar
ushermark
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Intel Arria 10 with dual-rank UDIMM EMIF

Hello. I am a newbie in developing software for Intel Arria 10 FPGA. I have a PCB with installed FPGA and trying to use EMIF. Unfortunately, I got an error on calibration stage. After some timing...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hello Mark,

    I have attached the example design in .qar file below. Please let me know if this design can fit into your board.
    Please share the Report DDR as snapshot below after the compilation process.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Mark,


I am glad to hear that your memory devices are passing the calibration.

I hope that you can move forward with this success.


Below are some hints that can help to configure the DDR in future :-

  • Always check the Calibration Report for any violation especially in timing analysis.
  • Double check the EMIF IP setting with memory device datasheet.
  • Refer to DDR scheme when placing the pin in IO Bank.
  • Testing with EMIF example design first.


I will transition this thread into community support. Feel free to open a new thread if you have a new question. Otherwise, the community users will continue to help you on this thread.


Thank you.

Regards,

Adzim