Forum Discussion
Intel Arria 10 with dual-rank UDIMM EMIF
- 3 years ago
Hello Mark,
I have attached the example design in .qar file below. Please let me know if this design can fit into your board.
Please share the Report DDR as snapshot below after the compilation process.
Hi Mark,
There is timing violation in your design. This will cause the failure during the calibration process.
May I know the device OPN that you used? And can you provide the pin placement as well?
I will try to generate an example design and share with you for debugging purpose.
Thanks,
Adzim
Hello Adzim,
I am using an unique board with installed FPGA that was developed by my company, so I cannot give much details about it.
Attaching pin planner .csv file.
Best regards,
Mark
- AdzimZM_Altera3 years ago
Regular Contributor
Hello Mark,
I have attached the example design in .qar file below. Please let me know if this design can fit into your board.
Please share the Report DDR as snapshot below after the compilation process.- ushermark3 years ago
New Contributor
Hello Adzim,
I have tested example design from your project. EMIF IP settings are working on my board. All 6 same type RAMs from different vedors have passed calibration.
Also, I tried to increase working frequency up to 1200MHz and it was still working. It took me around 1 month to find a proper settings and your solution finally give me a required result.
Do you have any hints that might help me to find a similar solution for different RAM types in the future?
Thank you very much for help!
Best regards,
Mark