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ushermark's avatar
ushermark
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Intel Arria 10 with dual-rank UDIMM EMIF

Hello. I am a newbie in developing software for Intel Arria 10 FPGA. I have a PCB with installed FPGA and trying to use EMIF. Unfortunately, I got an error on calibration stage. After some timing...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hello Mark,

    I have attached the example design in .qar file below. Please let me know if this design can fit into your board.
    Please share the Report DDR as snapshot below after the compilation process.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello Mark,


Do you have any feedback in this thread?


Regards,

Adzim


  • ushermark's avatar
    ushermark
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello Adzim,

    Sorry for delayed answer. I had no time to check it on previous week.

    I will attach Timing Analyzer results to this message. I believe, it says the same thing that I see from EMIF Debugger. I haven't tried to use this tool before, so I might miss something from it.

    The project is based on example design with modified parameters.

    Also, I am pretty sure that pins are correct, because the same project with different timings in EMIF IP has been used with different memories like UDIMM 1Rx8 non-ECC, RDIMM 2Rx8 ECC etc.

    Best regards,

    Mark