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ushermark's avatar
ushermark
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Intel Arria 10 with dual-rank UDIMM EMIF

Hello. I am a newbie in developing software for Intel Arria 10 FPGA. I have a PCB with installed FPGA and trying to use EMIF. Unfortunately, I got an error on calibration stage. After some timing...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    2 years ago

    Hello Mark,

    I have attached the example design in .qar file below. Please let me know if this design can fit into your board.
    Please share the Report DDR as snapshot below after the compilation process.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello Mark,


Do you see any timing violation in the Compilation report?

Especially in "emif_0|emif_0 " table that you can find in Timing Analyzer/Report DDR/*all model*


Are you using the example design or your own design?


The pin placement for address/command pins must be followed "DDR4 Scheme 4: Component/UDIMM/RDIMM".

I think the alert_n signal is suitable to be placed along with the DQS group.

Can you check the pin placement as well?


Regards,

Adzim