Forum Discussion
travisa
New Contributor
New ContributorIntegrating a Avalon FIFO IP to the PCIe DMA transfer example design for Arria 10 GX
Hi,
I am trying to stream in data from an external source (through QSFP+) to the DDR4 memory and then do a DMA transfer the data to a Computer through PCIe.
For that I would like to use a FIFO ...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi travisa,
The error may appear when changing some of the Avalon parameter in the IP.
The QSYS will check the IP and the interconnect system to connect the port.
But the change may reflect to the IP only and the interconnect still has the previous value.
Then the QSYS will ask the user for checking on that if the new value should be used.
You can follow the recommendation that has been provided from QSYS to resolve the problem.
For FIFO IP consent, you can direct to FIFO IP user guide for the details.
There should be some specs and supported features that have been described in the user guide.
LINK: https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/fifo-user-guide.html
Regards,
Adzim
