Integrating a Avalon FIFO IP to the PCIe DMA transfer example design for Arria 10 GX

Hi,

Thank you very much for recreating my problem and sending me the file. I tried compiling it and succeeded. I would like to ask some questions regarding this. So I am explaining the steps I followed to run the .qsys file and attaching relevant screenshots.

1. I worked in my DE5a-Net "CD/Demonstrations/PCIe_DDR4/" folder and opened PCIe_DDR4.qpf Quartus Project file opened the ep_g3x8_avmm256_integrated.qsys in the System Builder.

2. Changed Address unit from SYMBOLS to WORDS for Avalon MM Pipeline Bridge IP and Avalon MM Clock-crossing Bridge IP. This throws an error as shown in CaptureA1.PNG. Resolved the port mismatch manually to resolve the errors.

I have a question regarding this step. What is the real cause of the error "Port mismatch could not be auto resolved. Double click for manual resolution" and what is the recommended solution for this. I it just merge option by double clicking the error?

Also, is there any reason other than improving the IP timing for changing Address unit from SYMBOLS to WORDS

3. I have added the Avalon MM FIFO IP and Clock Bridge IP to the design.

(I really would like to know is there any specific reason you used clock bridge IP to clock FIFO IP, instead of the clock from Clock IP or Clock from Avalon-MM DMA Hard IP?)

4. Connecting the out slave of FIFO IP with the masters from m0 from Avalon MM Pipeline Bridge IP. This gives the memory overlap issue. Would you please remind me why we should change the address specifically to 0x1_0000_0000 or higher?

By changing address to what you suggested removes error messages. Then ran the Generate HDL (as seen in CaptureA9.PNG (do we want to worry about the warning messages as seen in screenshot?) and then successfully compiled the project.

I am planning to make a custom IP that create random bits that should stream through FIFO to DMA and which in turn DMA transferred to a PC through PCIe. I there any thing we should be cautious in creating a custom IP that creates bits and feeds to FIFO?. Thank you very much.