Forum Discussion

travisa's avatar
travisa
Icon for New Contributor rankNew Contributor
3 years ago

Integrating a Avalon FIFO IP to the PCIe DMA transfer example design for Arria 10 GX

Hi, I am trying to stream in data from an external source (through QSFP+) to the DDR4 memory and then do a DMA transfer the data to a Computer through PCIe. For that I would like to use a FIFO ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Sir,

Thank you for submitting your question in Intel Community.

I'm Adzim from Penang Global Application Engineer will assist you in this thread.

I've replicated the issues that you're facing and I think some settings in the Avalon Pipeline Bridge IP need to change.

  • There is an option that you can use under the Address section -> Use automatically-determined address width. It's ease the user to determined the address width.
  • I'm also advice you to use Address unit of WORDS. This can help the IP to improve the timing.

For the address overlapping issue, you can set the Base address of the Avalon FIFO Memory IP to 0x1_0000_0000 or higher to avoid the overlapping.

I hope that can resolve the problem.

Regards,

Adzim