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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Instantiate PCIe PIPE PHY in Stratix IV GX?

I'm trying to instantiate just the PCIe PIPE PHY in a Stratix IV GX part, for use with a non-Altera soft IP core. The mega-wizard utility seems to let me use the PCI Express Compiler to instantiate a...
im30naa's avatar
im30naa
Icon for New Contributor rankNew Contributor
4 years ago

Hi. I've instantiated a PCIe PIPE in Stratix V. Its PLL is locked and its tx_ready and rx_ready signals are also 1. Meaning that the phy is ready to work. However, when I initiate a RX Termination Detection to the PHY, it returns 3'b000 with pipe_phystatus = 1'b1 meaning that no receiver is present. Although I attach a device to it. So, what should I do? Thank you in advance.