Forum Discussion
Altera_Forum
Honored Contributor
17 years agoIt's pretty cleat, that the PCIe Dev Kit on-board DDR2 RAM can only be utilized as a whole, either 64- or 72-bit wide memory. The simulatanous access may be achieved by interleaving read and writes through the FIFO, that is used anyway inside the DDR2 controller. Writing full rows at each access, you can come near to the said theoretical througput of 48 GB/s.
As a first step, you may calculate your total througput requirements, design an access scheme and find out, if it's feasible.