Altera_Forum
Honored Contributor
18 years agoInquiry on Synthesis Report for Scaler 7.2
Hi,
I am working on the Scaler Example design using the MegaCore IPs and I have managed to compiled it using Signal Compiler Next I went to synthesize it and attached is the report I have gotten. However, I am a bit suspcious that the requirements doesn't seem to be very taxing. Why is this so?