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HBhat2's avatar
HBhat2
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6 years ago

Initial Data is missing in the receiver side of Stratix 10 Native PHY

Hi, We have developed a custom PCS for TBT3 (Thunderbolt-3) like protocol. I am able to test and receive a protocol specific packet continuously in stratix 10 SoC Dev kit. Going forwards, I need t...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi HPB,

Regarding your inquiry on the tLTD, for your information, the rx_ready will be asserted after the tLTD and digitalreset go low. Therefore, if you are sending data after rx_ready go high, I think it is not the cause to the data missed that you are observing. We can isolate this for the moment and revisit if required after we test with the simulation without custom PCS.

Thank you,

  • HBhat2's avatar
    HBhat2
    Icon for Contributor rankContributor
    6 years ago

    Hi @cheepinc_Intel​ ,

    Yes, I have done the PMA only simulation and done 2 types of simulation.

    1) Sending data before rx_ready asserts

    2)Sending data after rx_ready asserts

    and I observed that there is no data loss when I send the data after rx_ready gets asserted (type 2 simulation).

    All the previous simulations I carried out with my custom PCS is Type-1 simulation where our intention was there is no relation between TX and RX.

    And this is not a problem in our real hardware as the protocol does not send any data to Transmitter as soon as power up.

    Thank you for your clarifications.

    With Regards,

    HPB