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HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
6 years ago

Initial Data is missing in the receiver side of Stratix 10 Native PHY

Hi, We have developed a custom PCS for TBT3 (Thunderbolt-3) like protocol. I am able to test and receive a protocol specific packet continuously in stratix 10 SoC Dev kit. Going forwards, I need t...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi HPB,

As I understand it, you observe some data missing from the RX parallel data output in the simulation. To facilitate further debugging, would you mind to:

1. Create a simple test design without using your custom PCS. Try to send fix parallel data to the TX PMA and loopback to RX PMA to see if you are able to get back the same parallel data (with incorrect word boundary). You may not need to send 256. Probably 3 will do after the rx_ready go high. You may test this in Modelsim simulation.

2. If the design in #1 is able to replicate missing parallel data, please help to share with me the simulation files together with steps to replicate the simulation. I would like to take a look to get a better understanding.

3. Please share with me the Native PHY .ip file so that I can have understanding on your configuration.

4. What is the specific S10 device and Quartus version that you are using currently?

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin