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HBhat2's avatar
HBhat2
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6 years ago

Initial Data is missing in the receiver side of Stratix 10 Native PHY

Hi, We have developed a custom PCS for TBT3 (Thunderbolt-3) like protocol. I am able to test and receive a protocol specific packet continuously in stratix 10 SoC Dev kit. Going forwards, I need t...
HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
6 years ago

Hi,

I noticed that there is a "tLTD" timing, which is 4us minimum as per startix 10 device data sheet. Whether this "tLTD" causing the data miss in the receiver side?

If "tLTD" is the cause, then I should consider "tLTD" = 4us or 5us (minimum) ? Reason being, in L-tile user guide "tLTD" is being mentioed as "minimum duration of tLTD of 5us".

With regards,

HPB