In qsys,can PCIe IP receive write request that exceeds 512 bytes?

Thanks very much for your so detail reply.

The maxim clock is 74.25M 16bit video bus.So,the maxim data throughput is sure.

For the throughput,I think it's fine.For DMA uses PCIe 125M clock,and that one clock DMA can move up to 64bit data,in our case it moves 32bit data,4byte.(The video IP sends a 32bit YUYV color plane data)

"A large PCIe write is split into multiple requests each of typically (but negotiated) 128 bytes, a small number of which can be outstanding at any one time."

128bytes?According to the ug_pcie_guide doc,the Qsys support burst write to 512 bytes.According to PCIe spec,it is 4K bytes maxim.So,how does 128bytes come?

"a small number of which",you meant that just "SMALL NUMBER",such as you said transfer each video line(4k bytes) per time?that if the burst write is large,such as 4M Bytes,it will CAN'T be outstanding?

"I don't know exactly how the Avalon PCIe master side works - we've only used the slave (master is a small ppc)."

"Master" you mean the PCIe RC?or Transaction Initiator?

"Slave" you mean the PCIe EP?Or Transaction Completer?

Our case is that FPGA acts as PCIe EP,and perform DMA writing to TI's DSP(PCIe RC) after the Soc write control data to DMA engine,just like you said "there was a dma engine inside the PCIe block".

And thanks again for your suggestions that Transfer each video line one time, but I may think transfer 65535 bytes per time for that if I transfer each video line per time,that will cost more space and more PCIe cycles for sgdma descriptor.

Yes,I use a Avalon-ST DC FIFO for video buffer to avoid overflow.