In qsys,can PCIe IP receive write request that exceeds 512 bytes?

Thanks dsl.

And our case is that capture video (up to 1080P30)data and send to our TI' soc,one frame per time.

The reason I want to make FPGA send much more data ,such as 4,147,200 bytes,is that then the SOC(PCIe RC)can just write control data to FPGA,just once.

If FPGA burst writes 512 bytes per time,then then if we want to send one frame(1080P30 YUV 4:2:2)data to Our SOC,that is 4,147,200 bytes.The memory for descriptor is also so large that FPGA on-chip memory is not enough.

So,we want to send much more data one time.

Sorry for my bad english and I'm greenhand for FPGA field.

I still have two questions:

1>You meant that DMA/SGDMA can generate multile burst write to PCIe IP.

And if I make DMA/SGDMA to send much more data,how does it know to split the BIG data to the smaller burst write(such as 512 bytes write)?

2>For DMA/SGDMA transferring,what is the processing?

For example,the block is FIFO---->DMA/SGDMA--->PCIe.

The operation is to transfer 512 bytes from FIFO to PCIe.

first case,DMA/SGDMA move data to its internal FIFO first until the all data(512 bytes) is ready,and then transfer these to PCIe.

second case,DMA/SGDMA move data from FIFO to PCIe directly,and some times DMA/SGDMA doesn't move data when FIFO is empty,and until all data(512 bytes)is moved to PCIe.

Which case is right.

So sorry for many naive questions.

Expecting for any reply.

regards~