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Altera_Forum
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14 years ago

Improve performance of TSE on Stratix IV GX

Hello, I'm using the Standard design of Stratix IV on which I put the Nios II Simple Socket Server in order to receive incoming data from my other computer. I managed to establish a TCP/IP...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Thank you dsl,

I think that I'll leave the checksum if it's very recommended, I wouldn't like to do unrecommended things with my FPGA =)

I don't get the network time overlapping with the processing of previous/next. Do you mean that I should like unqueue the received packet and store them anyway even if they aren't like packet_t | packet_t+1 | packet_t+2 ?

If that's what you mean I can't do that because I need my packet to be chronologically ordered since it's a real time application.

I think that I won't create my own TCP/IP stack since it may be risky for my projet timeline.

Do you think that I can offload my 1440 bytes buffer using the Nios PIO?

I'd like my VHDL component to read that buffer 40 bytes by 40 bytes but it seems that the Nios II is way to slow.

I was thinking about storing these data into 10 differents FIFO but I'm not sure if it'll be fast enough.