Implement a Remote System Upgrade in FPGA fabric

Hi @YuanLi_S_Intel ,

Thanks for your following reply & sorry for raising other tickets - reason why I did that is because seen no solid complete answers to the previous ones. Will try to keep my main communication to this ticket from now, onwards unless something else new comes up unrelated to this one.

>> Yes, you may use MAX V for that. I don't see any issue in your use case unless you need to use some IP which the max10 has such as NIOS II.

Please see my latest comments :

1) So the data can be any data (doesn't need to be special passive). Does the PFL when it receives the parallel data/address sort this scheme out before the flash is programmed and can then passive configure successfully the Cyclone V FPGA ?

Sorry, to clarify also one of my previous statements. Wrt my other following ticket query, our remote host I2C has just links to our FPGA Cyclone V (and not direct links to the CPLD (MAX V)) before the new application image data gets forwarded to the CPLD (MAX V) with the use of the PFL IP core to program the flash :

Can we just implement our own logic circuitry within Cyclone V FPGA (without the use of the Remote Update IP) to receive remotely the new application image data (just chunk bare data) from our external host via I2C serially (and also convert it from Serial-2-Parallel within the Cyclone V FPGA) and then be able to load/update/store it to the PFL (PFL is within CPLD MAX V) new sector location as parallel data ready to program the flash?

2) Since we instantiate the PFL IP core within CPLD MAX V for FPP or PS configuration we can use the features in the PFL IP core to perform remote system upgrade. My understanding within the CPLD we will need to enable the extra 'pfl_nreconfigure’ port of the PFL & generate the fpga_pgn[2:0] via user logic to implement the state machine diagram as shown in Fig.16 pg20 of the Parallel Flash Loader Intel FPGA IP User Guide

Isn't this the case?

3) So, are we able to still achieve this data transfer via I2C to Cyclone V FPGA through to MAX V CPLD -> PFL_ip with the above suggested implementation use case ? Please re-confirm