Implement a Remote System Upgrade in FPGA fabric

Hi,

Please find my response below:

[1] Seen also in one of the documents that "Altera recommends storing only 1 application image at 1 sector boundary" as I try to implement above. Is this the case ?

Page 0 - Sector 0

Page 1 - Sector 1

Page 2 - Sector 2

<auto> mode will sort out the start addresses for each Page BUT is it better to store each Page into a different Sector boundary? Does eg <auto> do this ?

If the answer is <auto> can do anything and it ensures not writing on the address of the other SOF files and also on the address where the option bits is located in, that's fine. We can stick to using <auto> for each page & get the start addresses of each page generated automatically by the Quartus tool.xxx

Yes, only 1 design (1 SOF) can be stored in 1 page. If you have multiple FPGA to program in 1 chain, then you can have multiple SOF in 1 page.

For Auto mode, the Quartus II software aligns the pages on a 128-Kbyte boundary; for example, if the first valid start address is 0x000000, the next valid start address is an increment of 0x20000. I think it will not overlap the address.

2) So the data can be any data (doesn't need to be special passive). Does the PFL when it receives the parallel data/address sort this scheme out before the flash is programmed and can then passive configure successfully the Cyclone V FPGA ?

As long as you are programming into flash with POF generated from our Quartus programmer, then it can be configure the Cyclone V successfully.

3) Sorry, to clarify also one of my previous statements. Wrt my other following ticket query, our remote host I2C has just links to our FPGA Cyclone V (and not direct links to the CPLD (MAX V)) before the new application image data gets forwarded to the CPLD (MAX V) with the use of the PFL IP core to program the flash :

Can we just implement our own logic circuitry within Cyclone V FPGA (without the use of the Remote Update IP) to receive remotely the new application image data (just chunk bare data) from our external host via I2C serially (and also convert it from Serial-2-Parallel within the Cyclone V FPGA) and then be able to load/update/store it to the PFL (PFL is within CPLD MAX V) new sector location as parallel data ready to program the flash?

Yes, you can do that.

4) Since we instantiate the PFL IP core within CPLD MAX V for FPP or PS configuration we can use the features in the PFL IP core to perform remote system upgrade. My understanding within the CPLD we will need to enable the extra 'pfl_nreconfigure’ port of the PFL & generate the fpga_pgn[2:0] via user logic to implement the state machine diagram as shown in Fig.16 pg20 of the Parallel Flash Loader Intel FPGA IP User Guide

Isn't this the case?

Yes you are right.

4) So, are we able to still achieve this data transfer via I2C to Cyclone V FPGA through to MAX V CPLD -> PFL_ip with the above suggested implementation use case ? Please re-confirm

Yes you can.

Thank You.

Regards,

Bruce