Contributor
Regular ContributorHi,
Please find my response below:
[1] FPL? Do you mean PFL (Parallel Flash Loader) ?
Yes, it is Parallel Flash Loader (PFL).
[2] We will also require the 'Image Update Circuitry' functionality within our Cyclone V FPGA (wrt fig17 of the PFL Intel FPGA IP User Guide) and we will like if possible to use the 'Remote Update Intel FPGA IP' (option 1 - our preferred option BUT see below ..)
Otherwise (option 2) will have to implement our own User 'Image Update Circuitry' logic to implement this functionality. You confirmed that we can add other circuitry to implement the 'Image Update Circuitry' logic. Has anyone else implemented a similar design (option2)? Do you have any example design to suggest for the type of devices we are using ?
Yes, as stated above. User can create their own 'Image Update Circuitry' or use Intel Remote Update IP for remote updating functionality. Apologize that do we not have any example design for option 2.
[3] We are using FPP configuration mode 1Gb Flash 16 bits (instantiating an altera_paraller_flash_loader_0 ie not the version II ie altera_paraller_flash_loader_2) and will like to maintain this FPP configuration working. We instantiate the PFL IP core in the MAXV CPLD for Fast Passive Parallel (FPP) configuration and planning to use the features in the PFL IP core to perform Remote System Upgrade.
In Option1, can we use a Serial-to-Parallel conversion (S2P) to the serial output data and address of the 'Remote Update Intel FPGA IP' output serial Data/Address to generate parallel Data/Address to our parallel flash? And to use a S2P could the configuration device be a PS one or AS type from the list below of available configuration devices? I believe here it should be PS so when convert to parallel it will be still passive type. Please clarify here.
To use Remote Update IP, we need to select configuration mode in Quartus as Active Serial mode. So for this scenario, PS for configuration and AS for remote update, I would suggest to use the flash which are supported by both scheme.
You can find the list of flash devices supported by PFL IP:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf (Page 4)
Thank You.
Regards,
Bruce
ContributorWrt your reply statement
"To use Remote Update IP, we need to select configuration mode in Quartus as Active Serial mode. So for this scenario, PS for configuration and AS for remote update, I would suggest to use the flash which are supported by both scheme"
The Remote Update IP just asks which configuration device will be using? It does not ask to select whether is PS or AS scheme.
Our PFL we are using only supports Passive configuration scheme, not Active !
Our choice is to use the Remote Update IP for the remote updating functionality. It was my understanding that there is no idea of the type of configuration PS, FPP or PS in the Remote Update circuitry. It's just pure data & address lines going from RSU to the flash. Isn't this the case?
The issue with the Remote Update IP is that it does not support the flash device we are currently using. We are trying to create other architecture of flash to be compatible.
eg If we select for our Parallel Flash Loader (PFL) the following setup :
Target flash : Quad SPI
How many flash devices? 4
Quad SPI flash density: QSPI 256Mbit
ie (256Mbit * 4 -> 1Gbit)
& FPGA configuration scheme -> FPPx16 (It gives us this option here for this target flash) or PS (prefer to leave it as FPP. This is Passive support and not Active)
& for the Remote Update IP we choose MT25QU01G configuration device from the list of configuration devices, will this setup work with the above PFL setup ?
We don't have much choice wrt our PFL library. Our MAX V CPLD uses PFL configuring using Passive scheme (FPP) to do the configuration. We could change it to PS but it has to be Passive not Active.
ContributorI created a new project targeting Cyclone V 5CEBA5F23C8 device,
I parameterised the Remote Update IP with the following settings :
Which operation mode will you be using ? REMOTE
Which configuration device you will be using ? MT25QU01G
Enabled all 3 options :
Add support for writing configuration parameters
Add support for Avalon interface
Enable reconfig POF checking
Created the VHDL for this IP.
Added manually the generated .qip under synthesis directory to the Quartus project.
Compile/elaboration was ok BUT got the following Errors during Fitting :
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Error (169310): Design has remote update block "rsu_remote_update_0_remote_update_0:remote_update_0|altera_remote_update_core:remote_update_core|sd1", but the selected configuration scheme "Passive Serial" does not support remote update
>> The configuration device chosen 'MT25QU01G' from this warning looks to be detected as a PS one >> and this does not support remote update.
>> What configuration schemes does the Remote Update block offer? Only Active Serial (AS) ?
>> Please reconfirm.
--
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:00
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
I did not include any pin assignments but left the tool initially do default fitting. Was very surprised from the above 2nd error message (11802).
Looked at the 'Fitter Resource Usage Summary' and seen ALMS <1% usage, LABs 1%, Logic registers < 1%, I/O pins 49%, Remote Update blocks 100% (1/1 used). Cannot see any resources used > 100%. Why I get this error message "Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device"?
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Tried the same flow above but with the following parameter setups :
Which operation mode will you be using ? REMOTE
Which configuration device you will be using ? S25FL512
Unticked all 3 options below :
Add support for writing configuration parameters
Add support for Avalon interface
Enable reconfig POF checking
Still get the following error :
Error (169310): Design has remote update block "rsu_remote_update_0_remote_update_0:remote_update_0|altera_remote_update_core:remote_update_core|sd1", but the selected configuration scheme "Passive Serial" does not support remote update
Tried also : MX25L256, EPCS128, EPCQ128, EPCQ128A , MX66U1G under "Which configuration device you will be using ?" but still get the same error as above.
Noticed in the Fitter / Device options, the Configuration Scheme listed was : Passive Serial (not able to update). Did it detect this scheme from the Configuration device selected ?
How can I resolve this error ?
The quartus tool we are using is 20.1 Lite Edition (not the standard or Pro versions). Any issues with the Lite Edition ?
ContributorContributorWrt your reply statement :
"To use Remote Update IP, we need to select configuration mode in Quartus as Active Serial mode. So for this scenario, PS for configuration and AS for remote update, I would suggest to use the flash which are supported by both scheme"
OK. Selected the configuration mode in Quartus 20.1 Lite Edition as 'Active mode' and set the Remote Update IP parameter configuration device as 'MT25QU01G'. Managed to compile/elaborate/synthesize & go through fitter stage the Remote Update IP in a standalone project.
What do I do next?
I think the issue is that the Remote Update IP does not support any Passive Configuration scheme ! Is this the case ?
Our normal flow to configure the Cyclone V FPGA without RSU is FFPx16 configuration ie set the PFL (PFL is instantiated within our MAX V CPLD) parameters as follows :
Our on board Flash we are currently using and cannot change is: S29GL01GT, 1Gbit 128Mx8. Our PFL (altera_parallel_flash_loader) only supports PS or FPPx16 configuration scheme!
You suggested using a flash that supports both Active and Passive configuration schemes. Please elaborate further your statement here. Are there such flashes available?
We need to be able to store 2 more application images (image1 & image2) in the Configuration flash memory. Image0 is the golden or fallback image (factory image). Program the new image to the flash on-the-fly during normal system operation and able to re-configure the FPGA with either image, switch between images automatically in case of system error. and at the same time we will like to keep our configuration scheme FPPx16 that works.
If the RSU can support Passive Serial (PS) configuration scheme we can use a Serial-to-Parallel (16-bits) converter converting the serial data/addr into parallel (16bits) out for out Parallel flash loader.
Can someone please reply here ?
