Contributor
Regular ContributorHi,
Please find my response below:
[1] Can I simply implement the state machine shown in fig.16 (pg20) for the 'User logic' block shown in fig17 (pg21) to generate/control the fpga_pgm[2:0] & pfl_nreconfigure signals ?
I assume here that the 'User Logic' has to be designed by the user in vhdl and this is the state machine shown in fig16 (pg20). Please confirm.
Yes, you can.
[2] What is the reason for dotted connectivity line --- shown in fig17 from the PFL/flash back to the FPGA ?
FPL is actually interacting with flash to get the bitstream stored and program the FPGA.
[3] If the 'User Logic' within the CPLD can achieve the 'remote system upgrade' capabilities with the implemented state machine in fig16 (as stated above), what is the 'Image Update circuitry' block (ref, Fig17) reason within the FPGA? Could that be when using a Serial Configuration scheme and that block could implement the Remote System Upgrade for Serial Configuration devices only (eg instantiating the Remote Update Intel FPGA IP which as I believe from what I seen so far only supports Serial Configuration devices and not FPP or PS) ? Please comment here.
Fig16 states that we can use PFL IP to write images into flash and also perform reconfiguration to load new images into it. User will need to create their own user logic to remotely send the image to PFL. Whereas Fig17 indicates the component when Intel Remote Update IP is used.
[4] I understand that we may require the 'Watchdog timer reset circuitry' functionality within the FPGA and connectivity to the PFL. This can be implemented in VHDL within the Cyclone V FPGA and it's output connected to the pfl_reset_watchdog pin of the PFL. I just opened our Parallel Flash Loader II Intel FPGA IP (parallel_flash_loader_2_0) on the IP catalog and I could not see the pfl_reset_watchdog listed as an input port. Looked at all the options that could be enabled but could still not see that pin being listed. How do I enable the PFL_RSU_WATCHDOG_ENABLED option to see the pfl_reset_watchdog input pin been generated? Please comment here too.
You need to turn on the option during IP creation. The option will be available if you change the operating mode to "Flash Programming and FPGA configuration".
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf (Page 40)
Thank You.
Regards,
Bruce
ContributorHi Bruce,
Thanks for your reply so far.
Wrt your latest comments, will appreciate your latest review comments to the following :
>> [2] What is the reason for dotted connectivity line --- shown in fig17 from the PFL/flash back to >> the FPGA ?
>> FPL is actually interacting with flash to get the bitstream stored and program the FPGA.
FPL? Do you mean PFL (Parallel Flash Loader) ?
Page 19 of the Parallel Flash Loader Intel FPGA IP User Guide states :
"We can download a new configuration image from a remote location, store it in the
flash memory device, and direct the PFL IP core to trigger an FPGA reconfiguration to
load the new configuration image"
From your next statement ".. User will need to create their own user logic to remotely send the image to PFL" :
We will also require the 'Image Update Circuitry' functionality within our Cyclone V FPGA (wrt fig17 of the PFL Intel FPGA IP User Guide) and we will like if possible to use the 'Remote Update Intel FPGA IP' (option 1 - our preferred option BUT see below ..)
Otherwise (option 2) will have to implement our own User 'Image Update Circuitry' logic to implement this functionality. You confirmed that we can add other circuitry to implement the 'Image Update Circuitry' logic. Has anyone else implemented a similar design (option2)? Do you have any example design to suggest for the type of devices we are using ?
We are using FPP configuration mode 1Gb Flash 16 bits (instantiating an altera_paraller_flash_loader_0 ie not the version II ie altera_paraller_flash_loader_2) and will like to maintain this FPP configuration working. We instantiate the PFL IP core in the MAXV CPLD for Fast Passive Parallel (FPP) configuration and planning to use the features in the PFL IP core to perform Remote System Upgrade.
In Option1, can we use a Serial-to-Parallel conversion (S2P) to the serial output data and address of the 'Remote Update Intel FPGA IP' output serial Data/Address to generate parallel Data/Address to our parallel flash ? And to use a S2P could the configuration device be a PS one or AS type from the list below of available configuration devices? I believe here it should be PS so when convert to parallel it will be still passive type. Please clarify here.
The 'Remote Update Intel IP Configuration' devices it lists for our Cyclone V FPGA look to be all serial configuration ones & the 1st 4 look to be active serial! Is any type listed Passive Serial ? None of them below look to be parallel types. Please comment here too.
EPCS1/4/16/64/128
EPCQ16/32/6/128/256/512
EPCQL256/512/1024
EPCQ4A/16A/32A/64A/128A
MX25L128/256/512
MX25U128/256/512
MX66U1G/2G
S25FL128/256/512
MT25QL256/512
MT25QU256/512/01G
