Implement a Remote System Upgrade in FPGA fabric

Hi,

Please find my response below:

[1] Can I simply implement the state machine shown in fig.16 (pg20) for the 'User logic' block shown in fig17 (pg21) to generate/control the fpga_pgm[2:0] & pfl_nreconfigure signals ?

I assume here that the 'User Logic' has to be designed by the user in vhdl and this is the state machine shown in fig16 (pg20). Please confirm.

Yes, you can.

[2] What is the reason for dotted connectivity line --- shown in fig17 from the PFL/flash back to the FPGA ?

FPL is actually interacting with flash to get the bitstream stored and program the FPGA.

[3] If the 'User Logic' within the CPLD can achieve the 'remote system upgrade' capabilities with the implemented state machine in fig16 (as stated above), what is the 'Image Update circuitry' block (ref, Fig17) reason within the FPGA? Could that be when using a Serial Configuration scheme and that block could implement the Remote System Upgrade for Serial Configuration devices only (eg instantiating the Remote Update Intel FPGA IP which as I believe from what I seen so far only supports Serial Configuration devices and not FPP or PS) ? Please comment here.

Fig16 states that we can use PFL IP to write images into flash and also perform reconfiguration to load new images into it. User will need to create their own user logic to remotely send the image to PFL. Whereas Fig17 indicates the component when Intel Remote Update IP is used.

[4] I understand that we may require the 'Watchdog timer reset circuitry' functionality within the FPGA and connectivity to the PFL. This can be implemented in VHDL within the Cyclone V FPGA and it's output connected to the pfl_reset_watchdog pin of the PFL. I just opened our Parallel Flash Loader II Intel FPGA IP (parallel_flash_loader_2_0) on the IP catalog and I could not see the pfl_reset_watchdog listed as an input port. Looked at all the options that could be enabled but could still not see that pin being listed. How do I enable the PFL_RSU_WATCHDOG_ENABLED option to see the pfl_reset_watchdog input pin been generated? Please comment here too.

You need to turn on the option during IP creation. The option will be available if you change the operating mode to "Flash Programming and FPGA configuration".

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf (Page 40)

Thank You.

Regards,

Bruce