Contributor
ContributorWill appreciate if someone replies to my ticket. Very urgent please..
My latest review comments follow :
Wrt https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
The PFL IP core User Guide: Section 1.3.6 (pg19) wrt .pdf link above, states the following :
"When you instantiate the PFL IP core in the Intel CPLD for FPP or PS configuration, you
can use the features in the PFL IP core to perform remote system upgrade"
::
"We can achieve the remote system upgrade capabilities with the PFL IP core by controlling the fpga_pgm[2..0] and the pf1_nreconfigure ports via user defined logic" described in 1.3.6.2 (pg21) of the same PFL IP core User Guide.
Can I simply implement the state machine shown in fig.16 (pg20) for the 'User logic' block shown in fig17 (pg21) to generate/control the fpga_pgm[2:0] & pfl_nreconfigure signals ?
I assume here that the 'User Logic' has to be designed by the user in vhdl and this is the state machine shown in fig16 (pg20). Please confirm.
As stated already we have the FPP configuration scheme working with the PFL IP core including programming the MAX5 CPLD with the loader.pof that gives access to the flash (CFI_1Gb) and we will like to keep this functionality.
What is the reason for dotted connectivity line --- shown in fig17 from the PFL/flash back to the FPGA ?
If the 'User Logic' within the CPLD can achieve the 'remote system upgrade' capabilities with the implemented state machine in fig16 (as stated above), what is the 'Image Update circuitry' block (ref, Fig17) reason within the FPGA? Could that be when using a Serial Configuration scheme and that block could implement the Remote System Upgrade for Serial Configuration devices only (eg instantiating the Remote Update Intel FPGA IP which as I believe from what I seen so far only supports Serial Configuration devices and not FPP or PS) ? Please comment here.
I understand that we may require the 'Watchdog timer reset circuitry' functionality within the FPGA and connectivity to the PFL. This can be implemented in VHDL within the Cyclone V FPGA and it's output connected to the pfl_reset_watchdog pin of the PFL. I just opened our Parallel Flash Loader II Intel FPGA IP (parallel_flash_loader_2_0) on the IP catalog and I could not see the pfl_reset_watchdog listed as an input port. Looked at all the options that could be enabled but could still not see that pin being listed. How do I enable the PFL_RSU_WATCHDOG_ENABLED option to see the pfl_reset_watchdog input pin been generated? Please comment here too.
The Remote Update Intel FPGA IP includes the watchdog internal circuitry but it will be waste of IP usage if the other functionality related to remote system upgrade for serial configuration devices is not used.
